1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems having a plurality of data path elements operable independently to perform in parallel respective data processing operations specified by a program instruction, such as, for example, a so called very long instruction word (VLIW) and measures to reduce program code size for such systems.
2. Description of the Prior Art
VLIW data processors, or data processors having very long instruction words, explicitly encode multiple independent operations within each instruction thereby allowing instruction level parallelism. This can be very efficient in some data processing, for example in pixel processing. However, in other circumstances an instruction may not need to perform a plurality of independent operations in parallel and thus, the VLIW instruction will store “dontcare” or no-op values for all unused command buses. In such circumstances there is clearly an overhead in data storage associated with the portions of the instruction that are not being valuably used.
VLIW processors such as the TMS320C6xx and SC140 processors are advantageous in providing for highly parallel execution of data processing operations. However, as the complexity of processing operations to be performed steadily increases, the high program memory storage requirements associated with these VLIW processors become a significant disadvantage.
Aditya et al (Automatic Design of VLIW and EPIC Instruction Formats, Compiler and Architecture Research HPL-1999-94, April 2000) discloses a code size reduction method for use with VLIWs. In this method a set of instruction templates that are customised to a given application or set of applications are generated, which are narrower in width than the standard VLIW of the system. A template select field allows selection of the particular template. Each template has a number of operation slots defining a particular operation from a mutually exclusive set of operations and in this way an instruction format that may be narrower than the VLIW is generated. Aditya “Code size Minimization and Retargetable Assembly for Custom EPIC and VLIW Instruction Formats” ACM Transactions on Design Automation of Electronic systems, Vol. 5 No. 4, October 2000 also discloses a code size reduction method for use with VLIWs.